A readout chip, consisting of 32×32 square cells, has been designed in a 65 nm CMOS technology. The circuit will be bump bonded to a slim/active edge pixel sensor to form the first demonstrator for the PixFEL X-ray imager, envisaged for applications to experiments at the next generation X-ray FELs. The pixel pitch is 110 μm, for a total area of about 16 mm2. Different solutions for the readout channel, which includes a charge preamplifier, a time-variant filter and a 10 bit ADC, have been integrated in the chip. In particular, a couple of different versions for the time-variant processor have been implemented. The charge preamplifier is provided with four different gain settings, therefore improving the system capability to comply with photon energies in the 1 keV to 10 keV interval. This work, besides discussing in detail the readout channel and array architecture, will present the first results from the chip characterization.

(2017). PFM2: A 32x32 readout chip for the PixFEL X-ray imager demonstrator . Retrieved from http://hdl.handle.net/10446/118444

PFM2: A 32x32 readout chip for the PixFEL X-ray imager demonstrator

Comotti, D.;Grassi, M.;Manghisoni, M.;Re, V.;Traversi, G.;
2017-01-01

Abstract

A readout chip, consisting of 32×32 square cells, has been designed in a 65 nm CMOS technology. The circuit will be bump bonded to a slim/active edge pixel sensor to form the first demonstrator for the PixFEL X-ray imager, envisaged for applications to experiments at the next generation X-ray FELs. The pixel pitch is 110 μm, for a total area of about 16 mm2. Different solutions for the readout channel, which includes a charge preamplifier, a time-variant filter and a 10 bit ADC, have been integrated in the chip. In particular, a couple of different versions for the time-variant processor have been implemented. The charge preamplifier is provided with four different gain settings, therefore improving the system capability to comply with photon energies in the 1 keV to 10 keV interval. This work, besides discussing in detail the readout channel and array architecture, will present the first results from the chip characterization.
2017
Ratti, L.; Comotti, Daniele; Fabris, L.; Grassi, Marco; Lodola, L.; Malcovati, P.; Manghisoni, Massimo; Re, Valerio; Traversi, Gianluca; Vacchi, C.; Batignani, G.; Bettarini, S.; Casarosa, G.; Forti, F.; Morsani, F.; Paladino, A.; Paoloni, E.; Rizzo, G.; Benkechkache, M. A.; Dalla Betta, G. F.; Mendicino, R.; Pancheri, L.; Verzellesi, G.; Xu, H.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10446/118444
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