This work will discuss the design of a high-linearity, low dispersion injection circuit to be used for pixel-level calibration of detector readout electronics. The circuit allows for precise analog test of the pixel cell units already at the chip level, when no sensor is connected. Moreover, it provides a simple means for calibration of readout electronics once the detector has been connected to the chip. The circuit discussed here will be part of the readout chip for the DEPFET Sensor with Signal Compression which is currently under development for application at the European XFEL facility. Since two options for the detector readout are currently under investigation, two injection circuit architectures have been designed. The aim of the paper is to discuss the design guidelines for the calibration circuit and to present the relevant simulation results of the developed system which will be implemented in a 130 nm CMOS technology.

(2011). High accuracy injection circuit for pixel-level calibration of readout electronics . Retrieved from http://hdl.handle.net/10446/120956

High accuracy injection circuit for pixel-level calibration of readout electronics

Manghisoni, M.;Quartieri, E.;Traversi, G.
2011

Abstract

This work will discuss the design of a high-linearity, low dispersion injection circuit to be used for pixel-level calibration of detector readout electronics. The circuit allows for precise analog test of the pixel cell units already at the chip level, when no sensor is connected. Moreover, it provides a simple means for calibration of readout electronics once the detector has been connected to the chip. The circuit discussed here will be part of the readout chip for the DEPFET Sensor with Signal Compression which is currently under development for application at the European XFEL facility. Since two options for the detector readout are currently under investigation, two injection circuit architectures have been designed. The aim of the paper is to discuss the design guidelines for the calibration circuit and to present the relevant simulation results of the developed system which will be implemented in a 130 nm CMOS technology.
Manghisoni, M.; Quartieri, E.; Ratti, L.; Traversi, G.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10446/120956
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