Design and Performance of Analog Circuits for DNW-MAPS in 100-nm-scale CMOS Technology

This paper is concerned with the design criteria and the experimental characterization and simulation results relevant to front-end electronics in 130 nm CMOS technology for the readout of monolithic active pixel sensors (MAPS) using a deep N-well (DNW) as their collecting electrode. As compared to the conventional 3T scheme, the one proposed here lends itself to sparsified processing of the data directly at the pixel level and is expected to be able to deal with the large flow of information anticipated for future, high luminosity particle accelerators. The work will present a brief summary of the characterization results relevant to the first two DNW-MAPS prototypes, the Apsel0 and Apsel1 chips, focusing particularly on the front-end processor features and performances. Further developments in the design of the readout electronics are presently under way, in order to comply with power dissipation and spatial resolution constraints set by the experiments for the next generation colliders. Such developments include the design of a DNW-MAPS chip, with sparsified readout and time stamping capabilities, for application to the ILC vertex detector, which will be described in this work together with a selection of the relevant simulation results.