The goal of this work is to provide an extensive analysis of the noise performances which can be attained by detector front-end integrated circuits in the 0.13 µm CMOS node. To estimate the noise limits of a front-end system in this CMOS generation, the paper presents the results of measurements carried out on NMOS and PMOS devices fabricated in a commercial process. Parameters extracted from experimental data are used to define design criteria for noise optimization in the perspective of future experimental environments.
(2006). Design criteria for low noise front-end electronics in the 0.13 µm CMOS generation [journal article - articolo]. In NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH. SECTION A, ACCELERATORS, SPECTROMETERS, DETECTORS AND ASSOCIATED EQUIPMENT. Retrieved from http://hdl.handle.net/10446/20142
Design criteria for low noise front-end electronics in the 0.13 µm CMOS generation
Re, Valerio;Manghisoni, Massimo;Traversi, Gianluca
2006-01-01
Abstract
The goal of this work is to provide an extensive analysis of the noise performances which can be attained by detector front-end integrated circuits in the 0.13 µm CMOS node. To estimate the noise limits of a front-end system in this CMOS generation, the paper presents the results of measurements carried out on NMOS and PMOS devices fabricated in a commercial process. Parameters extracted from experimental data are used to define design criteria for noise optimization in the perspective of future experimental environments.| File | Dimensione del file | Formato | |
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