3D DNW MAPS for High Resolution, Highly Efficient, Sparse Readout CMOS Detectors

This work is concerned with the design and characterization of deep N-well (DNW) monolithic active pixel sensors (MAPS) fabricated in a vertical integration (3D) CMOS technology. These devices come as an evolution of DNW MAPS fabricated in a planar (2D) CMOS process, whose resolution, detection efficiency and charge collection efficiency are expected to improve as a result of the increased functional density provided by 3D integration technologies. The aim of the paper is to discuss the design guidelines for the front-end electronics and the readout architecture as compared to the case of a 2D CMOS technology and to present the relevant simulation results. Power consumption estimation also shows that the proposed solution has the potential to comply with the power dissipation constraints set for the vertex detector at the International Linear Collider.