In the scope of the ARCADIA project, a set of custom LVDS driver and receiver has been fabricated in a 110 nm CMOS technology for the ARCADIA first Main Demonstrator chip (MD1), a 512x512 monolithic, fully depleted pixel matrix. The link is designed to provide a data rate of 2 Gbps and implements a control over the driver current in order to meet the needs of a low-power mode foreseen for the MD1. This paper will present the results from the characterization of the receiver/driver in a loopback configuration, and compare them to simulations.

(2022). A 2 Gbps Custom LVDS Transceiver for the ARCADIA Project . Retrieved from https://hdl.handle.net/10446/233929

A 2 Gbps Custom LVDS Transceiver for the ARCADIA Project

Gaioni, L.;Manghisoni, M.;Re, V.;Traversi, G.
2022-01-01

Abstract

In the scope of the ARCADIA project, a set of custom LVDS driver and receiver has been fabricated in a 110 nm CMOS technology for the ARCADIA first Main Demonstrator chip (MD1), a 512x512 monolithic, fully depleted pixel matrix. The link is designed to provide a data rate of 2 Gbps and implements a control over the driver current in order to meet the needs of a low-power mode foreseen for the MD1. This paper will present the results from the characterization of the receiver/driver in a loopback configuration, and compare them to simulations.
Pezzoli, M.; Gaioni, Luigi; Manghisoni, Massimo; Ratti, L.; Re, Valerio; Traversi, Gianluca
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10446/233929
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