We describe the SystemC Process State Machines that we have defined, as a variation of the UML method state machines, to model the behavior of reactive processes of the SystemC language. They are part of a complete UML 2.0 profile for SystemC that we have developed to improve the SoC (System on a Chip) design flow in order to provide a modelling framework which allows high-level designing SoC components in the style of UML using the SystemC design primitives. © Springer-Verlag Berlin Heidelberg 2005.
(2005). Modelling SystemC process behavior by the UML method state machines . Retrieved from https://hdl.handle.net/10446/243229
Modelling SystemC process behavior by the UML method state machines
Scandurra, P.
2005-01-01
Abstract
We describe the SystemC Process State Machines that we have defined, as a variation of the UML method state machines, to model the behavior of reactive processes of the SystemC language. They are part of a complete UML 2.0 profile for SystemC that we have developed to improve the SoC (System on a Chip) design flow in order to provide a modelling framework which allows high-level designing SoC components in the style of UML using the SystemC design primitives. © Springer-Verlag Berlin Heidelberg 2005.| File | Dimensione del file | Formato | |
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