Charge signal processors in a 130 nm CMOS technology for the sparse readout of small pitch monolithic and hybrid pixel sensors

Hybrid pixel detectors are nowadays a robust and mature technology for particle detection as well as for medical and X-ray imaging, but the demands for improved performance for the next generation high energy physics experiments ask for the development of novel devices. Monolithic CMOS pixels have the potential to provide high granularity thin detectors as the sensor and the readout electronics are integrated in the same substrate. However, they suffer from a few limitations closely related to their working principle. 3D vertical integration has the potential of providing a performance breakthrough toward the design of fast, radiation tolerant and ultra thin CMOS radiation sensors. This work will discuss the design of analog circuits for processing the signals from small pitch monolithic and hybrid pixel detectors designed and fabricated in a planar 130 nm CMOS technology and in a 130 nm CMOS technology with vertical integration capabilities. Various solutions complying with different S/N ratio and detector capacitance constraints will be described in this paper by means of circuit simulations and experimental results.