This work presents the experimental results from the characterization of a high accuracy injection circuit to be used for in-pixel calibration of a large sensor matrix. The circuit was designed for the calibration of the pixel cell unit of a hybrid pixel but, in principle, can be used also for other kinds of detectors, e. g. deep N-well monolithic CMOS sensors. In the case of hybrid pixels, the injection circuit is particularly useful to test the functionality of the readout electronics already at the chip level, when no sensor is connected to the chip. Two injection techniques can be provided by the circuit: one for a charge sensitive amplification and the other for a transresistance readout architecture. The aim of the paper is to describe the architecture of the calibration circuit and to present the results from the characterization of the system, which has been implemented in a 130 nm CMOS technology.
(2011). Performance of a high accuracy injection circuit for in-pixel calibration of a large sensor matrix [conference presentation - intervento a convegno]. Retrieved from http://hdl.handle.net/10446/25644
Performance of a high accuracy injection circuit for in-pixel calibration of a large sensor matrix
QUARTIERI, Emanuele;MANGHISONI, Massimo
2011-01-01
Abstract
This work presents the experimental results from the characterization of a high accuracy injection circuit to be used for in-pixel calibration of a large sensor matrix. The circuit was designed for the calibration of the pixel cell unit of a hybrid pixel but, in principle, can be used also for other kinds of detectors, e. g. deep N-well monolithic CMOS sensors. In the case of hybrid pixels, the injection circuit is particularly useful to test the functionality of the readout electronics already at the chip level, when no sensor is connected to the chip. Two injection techniques can be provided by the circuit: one for a charge sensitive amplification and the other for a transresistance readout architecture. The aim of the paper is to describe the architecture of the calibration circuit and to present the results from the characterization of the system, which has been implemented in a 130 nm CMOS technology.File | Dimensione del file | Formato | |
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