In the deep n-well (DNW) monolithic active pixel sensor (MAPS) a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. This work is concerned with the design and characterization of DNW MAPS fabricated in a vertical integration (3D) CMOS technology. 3D processes can be very effective in overcoming typical limitations of monolithic active pixel sensors. This paper discusses the main features of a new analog processor for DNW MAPS (ApselVI) in view of applications to the SVT Layer0 of the SuperB Factory. It also presents the first experimental results from the test of a DNW MAPS prototype in the GlobalFoundries 130 nm CMOS technology.

Recent progress in the development of 3D deep n-well CMOS MAPS

TRAVERSI, Gianluca;GAIONI, Luigi;MANGHISONI, Massimo;RE, Valerio;
2012-01-01

Abstract

In the deep n-well (DNW) monolithic active pixel sensor (MAPS) a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. This work is concerned with the design and characterization of DNW MAPS fabricated in a vertical integration (3D) CMOS technology. 3D processes can be very effective in overcoming typical limitations of monolithic active pixel sensors. This paper discusses the main features of a new analog processor for DNW MAPS (ApselVI) in view of applications to the SVT Layer0 of the SuperB Factory. It also presents the first experimental results from the test of a DNW MAPS prototype in the GlobalFoundries 130 nm CMOS technology.
journal article - articolo
2012
Traversi, Gianluca; Gaioni, Luigi; Manazza, Alessia; Manghisoni, Massimo; Ratti, Lodovico; Re, Valerio; Zucca, Stefano
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10446/27963
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