This work is concerned with the design criteria and the experimental characterization of front-end electronics in a 65-nm CMOS technology for the readout of hybrid pixels and of monolithic active pixel sensors using a deep N-well as their collecting electrode. The work presents a summary of the experimental results relevant to a prototype chip, named Apsel65, focusing particularly on the front-end processor features and performance.
A 65-nm CMOS Prototype Chip With Monolithic Pixel Sensors and Fast Front-End Electronics
GAIONI, Luigi;MANGHISONI, Massimo;RE, Valerio;TRAVERSI, Gianluca
2012-01-01
Abstract
This work is concerned with the design criteria and the experimental characterization of front-end electronics in a 65-nm CMOS technology for the readout of hybrid pixels and of monolithic active pixel sensors using a deep N-well as their collecting electrode. The work presents a summary of the experimental results relevant to a prototype chip, named Apsel65, focusing particularly on the front-end processor features and performance.File allegato/i alla scheda:
| File | Dimensione del file | Formato | |
|---|---|---|---|
|
IEEE65nmGaioni.pdf
Solo gestori di archivio
Descrizione: publisher's version - versione dell'editore
Dimensione del file
1.43 MB
Formato
Adobe PDF
|
1.43 MB | Adobe PDF | Visualizza/Apri |
Pubblicazioni consigliate
Aisberg ©2008 Servizi bibliotecari, Università degli studi di Bergamo | Terms of use/Condizioni di utilizzo
