The high luminosity asymmetric e+e− collider SuperB, recently approved by the Italian Government, is designed to deliver a luminosity greater than 1036cm−2s−1 with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. An improved vertex resolution is required for precise time-dependent measurements and the SuperB Silicon Vertex Tracker will be equipped with an innermost layer of small radius (about 1.5cm), resolution of 10um in both coordinates, low material budget (<1% X0), and able to withstand a hit background rate of several tens of MHz/cm2. The ambitious goal of designing a thin pixel device matching these stringent requirements is being pursued with specific R&D programs on different technologies: CMOS MAPS, pixel sensors in vertical integration technology and hybrid pixels with small pitch and reduced material budget. The latest results on the characterization of the various pixel devices realized for the SuperB Layer0 will be presented.

(2011). 2D and 3D thin pixel technologies for the Layer0 of the SuperB Silicon Vertex Tracker [conference presentation - intervento a convegno]. Retrieved from http://hdl.handle.net/10446/31287

2D and 3D thin pixel technologies for the Layer0 of the SuperB Silicon Vertex Tracker

MANGHISONI, Massimo;RE, Valerio;TRAVERSI, Gianluca;GAIONI, Luigi;
2011-01-01

Abstract

The high luminosity asymmetric e+e− collider SuperB, recently approved by the Italian Government, is designed to deliver a luminosity greater than 1036cm−2s−1 with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. An improved vertex resolution is required for precise time-dependent measurements and the SuperB Silicon Vertex Tracker will be equipped with an innermost layer of small radius (about 1.5cm), resolution of 10um in both coordinates, low material budget (<1% X0), and able to withstand a hit background rate of several tens of MHz/cm2. The ambitious goal of designing a thin pixel device matching these stringent requirements is being pursued with specific R&D programs on different technologies: CMOS MAPS, pixel sensors in vertical integration technology and hybrid pixels with small pitch and reduced material budget. The latest results on the characterization of the various pixel devices realized for the SuperB Layer0 will be presented.
2011
Giorgia, F.; Avanzini, C.; Batignani, G.; Bettarini, S.; Bosi, F.; Casarosa, G.; Ceccanti, M.; Cervelli, A.; Forti, F.; Giorgi, M.; Mammini, P.; Morsa...espandi
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10446/31287
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