This work presents the design and characterization of Explorer-0, a Monolithic Active Pixel Sensor (MAPS) developed in the framework of the R&D activity for the upgrade of the Inner Tracking System (ITS) of the ALICE experiment at CERN. The Explorer-0 chip has been manufactured in the TowerJazz 180 nm CMOS Imaging Sensor process, based on a high-resistivity (rho > 1 k Omega.cm), 18 mu m thick, epitaxial layer. It contains different pixel designs with a variation of the collection electrode shape and pixel pitch (20 mu m and 30 mu m). The pixel circuit offers the possibility of varying the sensor bias and to decouple the read-out time from the charge integration time. Charge collection properties of the different pixel designs have been studied with respect to the sensor bias using a 5.9 keV X-ray source (Fe-55) and a 4 GeV/c electron beam. The radiation tolerance of this technology in view of the expected radiation levels foreseen in ALICE has been established as well. The sensor capacitance, which is a key parameter for a compact low-power front-end design, has been estimated. Based on these results, a second version of the Explorer chip has been designed and successfully tested. The latter has a lower contribution of the circuit to the overall input capacitance allowing for a higher sensor Signal to Noise Ratio (SNR).

(2013). Explorer-0: A Monolithic Pixel Sensor in a 180 nm CMOS process with an 18 µm thick high resistivity epitaxial layer . Retrieved from http://hdl.handle.net/10446/187177

Explorer-0: A Monolithic Pixel Sensor in a 180 nm CMOS process with an 18 µm thick high resistivity epitaxial layer

Mattiazzo, S.;
2013-01-01

Abstract

This work presents the design and characterization of Explorer-0, a Monolithic Active Pixel Sensor (MAPS) developed in the framework of the R&D activity for the upgrade of the Inner Tracking System (ITS) of the ALICE experiment at CERN. The Explorer-0 chip has been manufactured in the TowerJazz 180 nm CMOS Imaging Sensor process, based on a high-resistivity (rho > 1 k Omega.cm), 18 mu m thick, epitaxial layer. It contains different pixel designs with a variation of the collection electrode shape and pixel pitch (20 mu m and 30 mu m). The pixel circuit offers the possibility of varying the sensor bias and to decouple the read-out time from the charge integration time. Charge collection properties of the different pixel designs have been studied with respect to the sensor bias using a 5.9 keV X-ray source (Fe-55) and a 4 GeV/c electron beam. The radiation tolerance of this technology in view of the expected radiation levels foreseen in ALICE has been established as well. The sensor capacitance, which is a key parameter for a compact low-power front-end design, has been estimated. Based on these results, a second version of the Explorer chip has been designed and successfully tested. The latter has a lower contribution of the circuit to the overall input capacitance allowing for a higher sensor Signal to Noise Ratio (SNR).
2013
Kugathasan, T.; Cavicchioli, C.; Chalmet, P. L.; Giubilato, P.; Hillemanns, H.; Junique, A.; Mager, M.; Tobon, C. A. Marin; Martinengo, P.; Mattiazzo, Serena; Mugnier, H.; Musa, L.; Pantano, D.; Rousset, J.; Reidt, F.; Riedler, P.; Snoeys, W.; van Hoorne, J. W.; Yang, P.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10446/187177
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