This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of 50×50μm2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm2 pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.

(2017). A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC . In JOURNAL OF INSTRUMENTATION. Retrieved from http://hdl.handle.net/10446/84163

A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC

Gaioni, Luigi;Traversi, Gianluca;Re, Valerio;Mattiazzo, Serena;
2017-01-01

Abstract

This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of 50×50μm2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm2 pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.
2017
Paternò, A.; Pacher, Luca; Monteil, Ennio; Loddo, Flavio; Demaria, Lino; Gaioni, Luigi; De Canio, Francesco; Traversi, Gianluca; Re, Valerio; Ratti, L...espandi
(2017). A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC . In JOURNAL OF INSTRUMENTATION. Retrieved from http://hdl.handle.net/10446/84163
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/10446/84163
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